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PC Innovation Bus

PCI Local Bus Highlights

The PCI Local Bus was developed to enable PC innovation in: 
Performance: 
  • allow second to none graphics for PCs 
  • overcome standard bus limitations 
Function: 
  • e.g., multi-media, motion video at volume price points 
Cost: 
  • highly integrated systems 
  • lowest cost peripherals 
  • investment spanning multiple CPU generations 
by driving a component-to-component connection standard for PCs, to complement existing board-to-board connection standards. 

Performance features include:

  • Data bursting as normal operating mode - both read & write
  • Linear burst ordering
  • Concurrency support (deadlock, buffering solutions)
  • Low latency guarantees for real time devices
  • Access oriented arbitration (not time slice)

Cost features:

  • No connection glue; no external data buffers
  • Low pin count interface
  • Implementable in existing ASIC technologies

Reliability:

  • Thorough electrical design for multiple loads at 33MHz
  • Error detection, reporting

Flexibility:

  • Processor independent; peripherals off processor "treadmill"
  • Multi-media support
  • Compatible with existing expansion standards
  • Scaleability designed in from the beginning
  • Applicable from laptop to server

Protocol:

  • Multi-master; peer-to-peer
  • 32-bit multiplexed, processor independent
  • Low pin count; 45 slave; 47 master
  • Synchronous, 8-33 MHz (132 Mbytes/sec)
  • Variable length, linear bursting - read & write
  • Parity on address, data, command
  • Concurrency/pipelining support
  • Initialization hooks for auto-configuration
  • Arbitration: central, access oriented, "hidden"
  • 64-bit extention transparently interoperable with 32-bit

Electrical:

  • CMOS drivers; TTL voltage levels
  • 5V, 3.3V interoperable
  • Reflected wave, rail-to-rail signaling
  • Dynamic current/voltage specified for drivers
  • Optimized drivers minimize pwr/gnd requirements

  • Direct drive - no external buffers; comprehends connectors

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